The invention concerns a multiprocessor computer system, in particular for on-line, high volume, transaction and communication oriented, computing operations, which, especially with a view to such applications, comprises multiprocessing features which involve unprecedented connectivety power, processing power and extension power for meeting present and future needs for very large data processing systems.
Such systems are necessary for on-line processing of large volumes of data at high transaction rates. A case in point is automatic credit card systems or processing of telecommunication data where very large volumes of data very rapidly arrives at the system and these data volumes are to be sorted, preprocessed, recorded, subsequently processed etc.
In addition to these requirements on data processing, the data processing system must satisfy special requirements on fault-tolerance.
It has been realized for some time that to provide for fault-tolerance proper, several processor modules must work together on the data processing task so that the data processing function of a faulty module can temporarily be taken over by another module. The coupling of several processor modules as known has some serious drawbacks.
In a first prior art approach a plurality of general purpose computers, usually only two, are coupled by means of a shared memory. This has the drawback that the entire system breaks down in the event of errors in the memory, and that it is difficult to solve the contention problems which arise when a plurality of computers simultaneously want to communicate via the shared memory.
In another prior art approach a plurality of minicomputers are coupled by their input/output channels. This involves a relatively slow data transport, i.e. a small transfer bandwidth as well as relatively extensive amount of hardware which is to couple the minicomputers which were originally not designed for this application.
This prior art therefore provides no solution to the technical problem, and the same applies to the operating system associated therewith. In still another prior art approach a plurality of processor modules are coupled by means of interprocessor buses, each controlled by a special bus controller, to provide a multiprocessor system. Each of the known processor modules has a central processor unit with access to a memory, which is operatively connected to an input/output channel. A device controller may be connected to input/output channels of several processor modules.
The latter prior art approach is never the less vitiated by some of the above-mentioned drawbacks. Firstly, there are limits to the number of processor units that can be coupled on the interprocessor buses shared by all the processor modules because of a bandwidth problem which can only be solved by providing the multiprocessor system with such extensive hardware as will result in a poor utilization thereof and in a reduction in the transfer power because the handling of such hardware is timeconsuming. Moreover, its connectivity power, i.e. the capacity of the system of rapidly receiving large volumes of data, is reduced because the input/output channels have to share the memory with the Central Processing Units which in turn reduces the processing power which is additionally burdened by the participation of the Central Processing Unit in the transfer of data between the memory and the interprocessing buses. Though this prior art is particularly concerned with fault tolerance, it has moreover the drawback that an error in a device controller causes shut down of all the associated peripheral units. This deficiency is striking as device controllers in systems of present type constitute a predominant part of the entire system.
Conclusively it must be said that the problems of the prior art arose when the need for greater connectivity power and processing power was realized, because the fault tolerance immediately appeared as a prerequisite, which, as mentioned, calls for the cooperation of several processor modules. In the prior art approaches the efforts of obtaining fault tolerance have been at the expense of connectivity power and processing power such that extension power is almost an unknown concept. By this is meant that the number of Central Processing Unit systems can be increased so an extent unknown and impossible by the prior art, which particularly involves bandwidth limitation of multitransferring lines for interconnection of the multiprocessing unit systems.
The object of the invention is to provide a multiprocessor computer system which, is fault-tolerant of course and provides for a great improvement in connectivity power, processing power and extension power separately and in a manner so that the increase of one effect does not noticeably reduce the two other effects. Another object of the invention is to provide a fault-tolerant input/output structure for separate improvement of connectivity power.
Still another object of the invention is to provide a Multiprocessor Unit module for separate improvement of processing power in fault tolerant systems.
Yet another object of the invention is to provide a fault-tolerant intermemory communication network for separate improvement of extension power.